In conventional telecommunication switching centers, more particularly telephone switching centers, analog signals continuous in time are transmitted in transmission channels separated physically from one another. More recent telephone switching centers do not utilize the space-division, but instead use the time-division multiplex (TDM) principle, whereby analog signals discontinuous in time are transmitted. Moreover, wider interest is now developing in telephone switching systems wherein digital signals (likewise discontinuous in time) are transmitted. In this regard, pulse-code modulation (PCM) has gained particular importance wherein at a sequence of time instants the instantaneous values of the amplitudes of the voice signals are represented by binary words which are then transmitted.
The primary object of a PCM/TDM switching center lies in switching through the binary words appearing over the PCM receive TDM trunks leading to the switching center in time slots particularly allocated to the individual connections. In accordance with the 4-wire operation of the PCM/TDM trunks coming into the PCM/TDM switching center or emanating therefrom there is always involved switching on a 4-wire basis, i.e., during switching both directions of transmission must be considered separately. To achieve this, the same time slot within the pulse frame derived from the exchange pulse frame of the relevant switching center at the sending end is normally used for the transmission of binary words during a call over a PCM/TDM trunk switched on a 4-wire basis and connected to such a switching center (cf. Proc. IEE 111 (1964) 12, 1976-1980, 1976, right-hand column, middle).
A prerequisite for correct switching in a PCM/TDM switching center is that the binary words to be transmitted be timely available for through-connection. This requirement is not met from the outset since, as a rule, the individual PCM/TDM trunks leading to a PCM/TDM switching center of a PCM telecommunication network have different delay times which, furthermore, are subject to temperature-dependent variations. Therefore, the bit clock pulses of the individual PCM/TDM switching centers will not coincide with one another without special provision.
To provide for the above prerequisite, three problems must basically be solved: Small phase variations ("jitters") occurring on the transmission circuit must be eliminated; the bit rate differences between signals transmitted over differently directed PCM/TDM trunks must be compensated; and, a pulse frame compensation must be performed ("isochronous mode") in order that all time slots having the same ordinal number coincide with one another with respect to time within the pulse frame under consideration in the incoming and outgoing directions. Thus the switching of connecting paths for both directions of transmission may take place simultaneously.
The first problem can be solved by means of a clock signal receiver, e.g., in the form of an oscillatory circuit excited by the transmitted bits determining the clock pulse rate of the bits regenerated therewith (Proc. IEE 113 (1966)9, 1420-1428, 1422; Reports on Telephone Engineering, Siemens A. G., 5 (1969)1, 48-59, 51).
The last mentioned problem can be solved by inserting approximately proportioned delay lines into the individual receive PCM/TDM trunks leading to the individual PCM/TDM switching centers, through which the transit time delay on the relevant PCM/TDM trunk is extended to a whole multiple of the frame period of the information bits. Thus, the pulse frames on all the PCM receive TDM trunks leading to the relevant PCM/TDM switching center coincide with one another with respect to time as well as with the pulse frames of all the transmit PCM/TDM trunks emanating from said switching center, as provided by the exchange pulse frame of the relevant PCM/TDM switching center (cf. BSTJ, XXXVIII (1959)4, 909-932, 922; Proc. IEE, 111(1964)12, 1976-1980, 1976, right-hand column, above; Proc. IEE, 113 (1966)9, 1420-1428, 1421, top of column 1; Reports on Telephone Engineering 5 (1969)1, 48-59, 52, 53). In connection with the above frame compensation, a compensation of temperature-dependent transit-time delay variations may be carried out simultaneously (cf. Proc. IEE, 113 (1966)9, 1420-1428, 1421, right-hand column; Reports on Telephone Engineering 5 (1969)1, 48-59, 53).
Various approaches are known for compensating for bit rate differences (cf. Proc. IEE, 113, (1966)9, 1420-1428, 1421; Reports on Telephone Engineering 5 (1969)1, 48-59, 51).
In the case of the asynchronous (heterochronous) mode, each PCM/TDM switching center has its own independent clock generator, and each receive TDM trunk ends in what is known as a pulse-frame storage, whose storage capacity corresponds to the number of bits per pulse frame. The binary words received are retained long enough in the storage to fit into the pulse frame of the PCM/TDM switching center concerned (the pulse frame storage performs at the same time the pulse frame compensation referenced above).
In the quasisynchronous (dummy bit) mode, the PCM/TDM switching centers of a PCM telecommunication network have their own independent clock generators, but the information bit rate, i.e., the mean number of information-carrying bits per second, is made equal for all PCM/TDM switching centers by compensating for the difference between the bit clock rates of the individual PCM/TDM switching centers and the common information bit rate by inserting bits without information ("dummy bits").
In the servosynchronous (homochronous, master-slave) mode, a common clock generator determines the bit rate of the individual PCM/TDM switching centers of a PCM telecommunication network.
Finally, in the autosynchronous mode, the individual PCM/TDM switching centers have individual clock generators which, however, are not independent of one another, but synchronize one another, for example, according to what as known as the phase-averaging principle.
As generally known, in the individual switching centers of a PCM telecommunication network, phase discriminators allocated to the individual lines are assigned to the incoming TDM trunks. These phase discriminators are energized at their inputs by a pulse train corresponding to the respective line bit clock pulse and by a pulse train corresponding to the exchange bit clock pulse of the switching center concerned. The phase discriminator output signals corresponding to the phase shift between the line clock pulse and exchange clock pulse, combined over a sum or mean value producing element, form the control signal for the frequency control of the exchange clock pulse oscillator. In this regard, the phase shifts may be caused by different clock frequencies of the clock oscillators provided in the individual switching centers of the telecommunication network and/or by fluctuations in the line-delay times.
A commonly known technique (cf. Electronics and Communications in Japan (ECJ) 49 (1966) 11, 165) for dealing with variations in line delay times is to employ as a pulse train corresponding to the line bit clock pulse or exchange bit clock pulse a pulse frame whose pulse repetition frequency is a submultiple of the bit clock frequency. This is carried out such (cf. ECJ 49(1966) 11, 167) that a pulse generated by a pulse frame detector is fed into a bistable circuit performing the phase comparison in a particular phase of the first time slot of each pulse frame of the incoming TDM trunk and a pulse in a particular phase of the mean time slot of each pulse frame of the switching center concerned. It may further be carried out such (cf. Nachrichtentechnische Zeitschrift (NTZ) (1970)5, 257-261) that in the individual switching centers of a PCM telecommunication network line bit clock pulses are obtained, with the aid of the oscillatory circuits, from the incoming PCM/TDM trunks. The phase shifts of the line bit clock pulses referred to the exchange bit clock pulses of the switching center concerned cause the control of the clock oscillators supplying the exchange bit clock pulse. The line bit clock pulse and exchange bit clock pulse are fed into two frequency dividers which start the frequency division. It is preferable that the line bit clock pulses and exchange bit clock pulses be displaced from one another by 180.degree. prior to frequency division. A phase comparison is then carried out between the frequency divider outputs by means of a bistable circuit. The DC mean value of the output signal of the bistable circuit is proportional to the phase difference and, thus, to the integral of a frequency difference, i.e., the difference between line clock frequency and exchange clock frequency. The output signals of all the bistable circuits allocated to individual lines are added via (generally identical) resistors for producing the mean value and smoothed by means of an RC network. The latter smoothed voltage varies the clock frequency of the exchange clock oscillator over a silicon or varactor diode.
The resetting edge of the exchange clock pulse for the frequency divider acts on the count inputs of the individual bistable circuits allocated to the two bistable circuit fields. If a line clock pulse fails, the associated bistable circuit runs as a counter having a duty cycle ratio of 1:1, thereby yielding a control voltage corresponding to an agreement between line clock frequency and exchange clock frequency. The oscillator frequency which is set when all the bistable circuits have a duty-cycle ratio of 1:1 is termed oscillator no-load frequency or clock frequency of the non-controlled clock oscillator.
In connection with the 180.degree. displacement referenced above, such a frequency-control range is aspired to and achieved (cf. ECJ 49(1966)11, 168) with the determination indicated above of the pulse repetition frequency of the pulse trains corresponding to the line bit clock pulse or exchange bit clock pulse. The control range is subject to the actual phase comparison in such a way that the bit clock frequency is a multiple of the pulse repetition frequency. Both through the specified frequency tolerances of the phase difference caused in the network nodes (switching centers or route regenerators) of the TDM telecommunication network of existing clock pulse oscillators and through the expected delay-time variations, phase differences between line clock pulses and exchange clock pulses in the ongoing control procedure caused on the TDM trunks interconnecting the network nodes are detected without requiring the control operating point to leave the area of a sawtooth-shaped phase comparison characteristic.
Two quantities are of interest for the statistical network condition: the departure of the final, radiated frequency common to all the network nodes from a predetermined normal frequency and the phase differences (also called absolute phase difference or phase distortion) between line clock pulse frame and exchange clock pulse frame; both depend on the frequency tolerances of the non-controlled clock pulse oscillators, i.e., of the frequency differences between no-load frequency and nominal frequency, and on the variations in the line delay times. The influence of these two reference variables on the system is likewise determined by the response characteristic provided by the quotient of (caused) clock frequency variation and (causing) phase difference (cf. Nachrichtentechnische Fachberichte (NTF) 42(1972), 311-319, 314). The final, radiated frequency or the departure thereof from the nominal frequency is determined by two components, i.e., by a first component which, regardless of response characteristic, depends on the frequency drifts of the non-controlled oscillators from the nominal frequency, and by a second component which is proportional to the response characteristic and to fluctuations in the delay times. The absolute phase difference is likewise determined by two components, i.e., by a first component, which is proportional to the frequency drifts of the non-controlled oscillators from the nominal frequency and inversely proportional to the response characteristic, and by a second component which is only determined by the delay time variations independently of the response characteristic.
If it is desired to minimize the influence exerted by line delay time variations on the clock frequency, this may be achieved by selecting an appropriately small response characteristic. However, large absolute phase differences may result from the stabilizing of frequency variations. Such large absolute phase differences, particularly in the case of chain-like networks may be caused if, for reasons or compatibility with asynchronous telecommunication networks, a high degree of frequency accuracy must be had. However, such large absolute phase differences between link clock pulse frame and exchange clock pulse frame require, particularly in the case of synchronization of superordinate systems, i.e., systems having multiplied clock frequencies, appropriate buffer storage capacities in the individual switching centers of the PCM telecommunication network to avoid loss of information. This has been found to be undesirable in practice even though, in principle, this might be insignificant in the presence of pulse frame storages receiving a full pulse frame at the end of the individual incoming PCM/TDM trunks.
The difficulties mentioned hereinabove are obviated by a circuit arrangement of known construction for the mutual synchronization of the exchange clock pulse oscillators provided in the network nodes of a TDM telecommunication network, (See U.S. Pat. No. 3,869,579). In the latter arrangement there is provided in each network node an exchange-clock frequency divider energized from the exchange clock pulse and trunk-clock frequency dividers energized from the trunk clock pulses provided on the TDM trunks coming in the network node, whereby the trunk-clock frequency dividers, after a possible reference phase regeneration, operate with a displacement in time of about 180.degree. in relation to the exchange-clock frequency divider. The output signals from the individual trunk-clock frequency dividers are transferred in conjunction with the output signal of the exchange-clock frequency divider to phase discriminators allocated to individual lines. The output signals of said phase discriminators are combined in a sum or mean value building element forming the control signal for the frequency control of the exchange-clock oscillator within its frequency control range.
In this prior art circuit arrangement, in addition to a first synchronizing circuit comprising exchange-clock and trunk-clock frequency dividers, phase discriminators, and a sum or mean value producing element with a control range quantity corresponding to the phase difference caused by the maximum occurring no-load frequency difference of the clock oscillators of two network nodes, whereby a reference phase regeneration commences if the control range quantity is exceeded, there is provided an appropriate second synchronizing circuit having exchange-clock and trunk-clock frequency dividers and phase discriminators with a region of operation corresponding to the phase difference provided by the sum of the aforementioned phase difference and the maximum delay time oscillation on a TDM trunk connecting two network nodes. By this means, the second synchronizing circuit subordinates an additional signal to the control signal supplied by the first synchronizing circuit. In the case of a positive difference between the exchange-clock phase and the mean trunk-clock phase, or in the case of a positive difference between the exchange-clock phase and the phase of at least one trunk clock exceeding a predetermined limit value, this additional signal defines at least one frequency control range lying under the oscillator no-load frequency. In the case of a negative difference between the exchange-clock phase and the mean trunk-clock phase, or in the case of a negative difference of less than a predetermined limit value between the exchange-clock phase and the phase of at least one trunk signal, the additional signal defines at least one frequency control range lying above the oscillator no-load frequency, the frequency of the exchange-clock oscillator in the frequency control range being controlled by the control signal supplied by the first synchronizing circuit.
The above described circuit arrangement which is based on the principle of gradual introduction of phase shifts of suitable direction in cooperation with reference phase regenerations brought about selectively and by defined frequency-control-range shifts in a network node, by which relatively large phase differences between exchange-clock pulse frame and trunk-clock pulse frame may gradually be broken down or avoided altogether. It is capable of eliminating the influences of delay line variations on the final radiated clock frequency without the necessity of or reducing the response characteristic. In fact the response characteristic may be quite as large as is necessary to limit absolute phase differences due to drifts of the oscillator no-load frequencies from the nominal frequency without allowing phase shifts caused by delay time variations to affect the final radiated clock frequency.
However, as is generally known, the influences of delay time variations on the final radiated clock frequency may, in principle, likewise be removed by deliberately bringing about reference phase regenerations, because reference phase regenerations alone eliminate a phase difference between trunk clock and exchange clock caused by a preceding delay time variation for the phase comparison underlying the frequency control and, with it, also for the frequency control itself. They allow the continued existence of the variation of the absolute phase difference proportional to the delay time variation. Accordingly, reference phase regenerations likewise cause the removal of a comparison phase difference resulting from a no-load frequency difference and bringing about the frequency control and, with it, a momentary interruption of the frequency control procedure until a new reference phase difference has been built up as a result of the existing no-load frequency difference. The reactivated existing absolute phase difference is increased accordingly, thereby providing an absolute phase drift which is proportional to the reference phase difference brought about by the maximum no-load frequency difference and to the number of reference phase regenerations.
It is generally known (West German Pat. No. 2,149,911 ) that reference phase regenerations are initiated when predetermined phase difference limits are exceeded as a result of the phase comparison underlying the frequency control. Thus, the phase difference limits determine, in accordance with the response characteristic, the limits of the frequency control range for the exchange clock pulse oscillator concerned. With a given response characteristic, the frequency control signal obtainable in a network node, as a result of the addition of the individual phase comparator output signals and, accordingly, also the frequency control range, are a function of the number of phase comparators effectively allocated to individual lines. Thus, they are a function of the network configuration.
In principle, different frequency-control-range variables of the individual network nodes do not stand in the way of a common final radiated clock frequency, but allow a momentary excursion of the clock frequency of the exchange clock pulse oscillator from the limits of the frequency control range of the exchange clock oscillator of another network node. Thus, they are capable of slowing the buildup of the telecommunication network to a final radiated clock frequency, so that by that time in the network nodes there may be a strong increase in the absolute phase differences between trunk-clock pulse frames and exchange-clock pulse frames coupled with a loss of information. Thus, it is desirable that the individual network nodes have the same frequency control ranges, which can be achieved by adjusting the response characteristic or the phase-difference limits independently of the network configuration; this adjustment, however, stands in the way of the normally desired uniformity in dimensioning of the individual network nodes.
It is, therefore, an object of this invention to provide a method and apparatus for the mutual synchronization of exchange clock oscillators which avoids the foregoing problems.